Recent News

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FTG's Seyong Lee wins IEEE CS TCHPC Award for Excellence for Early Career Researchers in HPC

FTG's Seyong Lee won the 2016 IEEE CS TCHPC Award for Excellence for Early Career Researchers in High Performance Computing: “In recognition of outstanding contributions in the field of high performance computing within 5 years of receiving a PhD degree." Recipients of the 2016 IEEE CS TCHPC Award for Excellence for Early Career Researchers in High Performance Computing will receive an award at SC16 on Thursday, Nov 17. 

See the announcment for IEEE CS at http://www.computer.org/web/pressroom/tchpc-award-2016 

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ORNL Creates a Programming System for Non-Volatile Main Memory Systems

4 Oct 2016  – Non-volatile memory (NVM) is playing a more important role in the memory architectures of HPC systems as illustrated by recent deployments and procurements. Yet there exist neither standard language constructs nor portable programming systems that provide support for these types of emerging memory architectures.

ORNL Develops an OpenACC-to-FPGA Translation Framework for High-Performance Reconfigurable Computing

13 May 2016 – A new paper entitled, "OpenACC to FPGA: A Framework for Directive-based High-Performance Reconfigurable Computing" describes how the Future Technologies Group at Oak Ridge National Laboratory (ORNL) is attacking the well-known programmability and performance portability challenges of Field Programmable Gate Arrays (FPGAs). The researchers have extended the standard, portable OpenACC specification for FPGAs and evaluated it with a prototype implementation, demonstrating that OpenACC programs can be directly compiled for FPGAs.

New FTG paper surveys approximate computing techniques

 A new FTG paper presents a survey of approximate computing techniques and has been highlighted on InsideHPC. Published in ACM Computing Surveys 2016, A Survey Of Techniques for Approximate Computing reviews nearly 85 papers on approximate computing in CPU, GPU and FPGA and various processor components (e.g. cache, main memory), along with approximate storage in SRAM, DRAM/eDRAM and non-volatile memories, e.g.

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New FTG report surveys asymmetric multicore processors

A new paper from FTG surveys asymmetric multicore processors, and has been highlighted on insideHPC. The paper reviews nearly 125 papers and has been accepted in ACM Computing Surveys 2015. Asymmetric multicore processors feature cores of different types (e.g. big and LITTLE) in the same processor and some commercial examples of them are Qualcomm Snapdragon 810, Samsung Exynos 5 Octa and Nvidia Tegra X1. 

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FTG members present automated approach for characterizing communication patterns at HPDC'15

Three Future Technologies Group members recently presented 'Automated Characterization of Parallel Application Communication Patterns' at the 24th International ACM Symposium on High-Performance and Distributed Computing (HPDC'15) in Portland, Oregon in June, 2015.  The paper describes an approach that uses automated search and a library of communication patterns to identify and parameterize a collection of patterns that best explains an MPI application's observed communication behavior.  Philip Roth presented the work on behalf of his co-authors, Jeremy Meredith and Jeffrey Vetter.

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FTG presentation on performance modeling selected as ‘Best Presentation’ at Exascsale Application and Software Conference in Edinburgh

24 Apr 2015 – This week, at the Exascale Application and Software Conference in Edinburgh, Scotland, the audience voted the FTG presentation on performance modeling as the conference’s Best Presentation. Jeffrey Vetter presented ‘Exploring Emerging Technologies in the Extreme Scale HPC Co-Design Space with Holistic Performance Modeling’ that discusses the importance of using performance modeling in the design of upcoming Extreme Scale platforms. The award was presented at the conference banquet at the The Royal College of Surgeons.

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DESTINY 3D cache modeling tool released

Oak Ridge National Lab, Penn State, and UCSB are pleased to announce the release of DESTINY (a 3D dEsign-Space exploraTIon tool for SRAM, eDRAM and Non-volatile memorY). DESTINY is a tool for modeling both 2D and 3D caches designed with five prominent conventional and emerging memory technologies: SRAM, eDRAM (embedded DRAM), PCM (or PCRAM), STT-RAM (or STT-MRAM) and ReRAM (or RRAM). DESTINY is intended to be a comprehensive tool, extending the capabilities of CACTI, CACTI-3DD, and NVSim, on which DESTINY is based. It can be used to model technology devices ranging from 22nm to 180nm.

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SC14 paper tapped as Best Student Paper Finalist

A FTG paper on analytical modeling of application resiliency was selected as a Best Student Paper Finalist at SC14 http://sc14.supercomputing.org/schedule/event_detail?evid=pap192. The paper, entitled "Quantitately Modeling Application Resilency with the Data Vulnerability Factor," introduces a pragmatic, data-driven methodology to analyze application vulnerability based on a novel resilience metric: the data vulnerability factor (DVF).

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FT researcher organizes data intensive workshop at SC14

Philip C. Roth, member of the ORNL Future Technologies Group since 2004, is part of the team organizing the 2014 Data Intensive Scalable Computing Systems (DISCS-2014) workshop at SC14.  The workshop focuses on the intersection between traditional high performance computing and data intensive computing, and SC continues to be the perfect conference to host the workshop because it draws substantial numbers of attendees from across the globe interested in HPC and/or data intenstive computing.

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FT researchers contribute to 2012 CScADS data workshop

Future Technologies Group members Philip Roth and Jeremy Meredith contributed to the 2012 CScADS workshop on Scientific Data and Analytics for Extreme-scale Computing, held July 30-August 2 at the Snowbird Ski & Summer Resort in Utah.  Roth served on a panel titled "The effect of emerging architectures on data science," though he also included content on analyzing and visualizing performance data in his panel presentation.   Meredith's work on a new scientific visualization and analysis library called EAVL was described in a presentation given by David Pugmire (also of ORNL).

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Future Tech researcher contributes to Cluster 12 conference

A paper by Chao Chen, Yong Chen (former Future Tech postdoc and now on the faculty at Texas Tech University), and current Future Tech group member Philip Roth has been accepted to be presented at IEEE Cluster '12 in late September in Beijing, China.  The paper, titled "DOSAS: Mitigating the Resource Contention in Active Storage Systems," quantifies the negative impact of contention in Active Storage systems and proposes a new approach for alleviating that negative impact.

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Meredith presents new geometric material interface reconstruction algorithm at Eurographics/IEEE Symposium on Visualization

Jeremy Meredith of ORNL’s Future Technologies group will present a new material interface reconstruction algorithm at EuroVis 2010, the Eurographics/IEEE Symposium on Visualization. This type of algorithm is used for generating geometric interfaces from material volume fraction data used in scientific applications, and is critical for a variety of visualization and analysis tasks. The paper, “Visualization and Analysis-Oriented Reconstruction of Material Interfaces”, by Meredith and collaborator Hank Childs from UC Davis and LBNL, evaluates this method against competing techniques.

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