MASTER: A Technique for Improving Energy Efficiency of Caches in Multicore Processors

Colloq: Speaker: 
Sparsh Mittal
Colloq: Speaker Institution: 
Iowa State University
Colloq: Date and Time: 
Thu, 2013-04-18 10:00
Colloq: Location: 
5700 L202
Colloq: Host: 
Jeffrey S. Vetter
Colloq: Host Email: 
vetter@ornl.gov
Colloq: Abstract: 
Large power consumption of modern processors has been identified as the most severe constraint in scaling their performance. Further, in recent CMOS technology generations, leakage energy has been dramatically increasing and hence, the leakage energy consumption of large last-level caches (LLCs) has become a significant source of the processor power consumption. This talk first highlights the need of power management in LLCs in the modern multi-core processors and then presents MASTER, a micro-architectural cache leakage energy saving technique using dynamic cache reconfiguration. MASTER uses dynamic profiling of LLCs to predict energy consumption of running programs at multiple LLC sizes. Using these estimates, suitable cache quotas are allocated to different programs using cache-coloring scheme and the unused LLC space is turned off to save energy. The implementation overhead of MASTER is small and even for 4 core systems; its overhead is only 0.8% of L2 cache size. Simulations have been performed using an out-of-order x86-64 simulator and 2-core and 4-core multi-programmed workloads from SPEC2006 suite. Further, MASTER has been compared with two energy saving techniques, namely decay cache and way-adaptable cache. The results show that MASTER gives the highest saving in energy and does not harm performance or cause unfairness. Finally, this talk briefly shows an extension of MASTER for multicore QoS systems. Simulation results confirm that a large amount of energy is saved while meeting the QoS requirement of most of the workloads.
Colloq: Speaker Bio: 
Sparsh Mittal is a PhD candidate at Iowa State University.