A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems

TitleA Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems
Publication TypeJournal Article
Year of Publication2016
AuthorsMittal, Sparsh, and Vetter Jeffrey
JournalIEEE Transactions on Parallel and Distributed Systems (TPDS)
Volume27
Issue5
Pagination1524-1536
Date Published05/2016
Keywords3D memory, cache, classification, compaction, compression, data redundancy, extreme-scale computing systems, main memory, Non-volatile Memory, Review
Abstract

As the number of cores on a chip increase and key applications become even more data-intensive, memory systems in modern processors have to deal with increasingly large amount of data. In face of such challenges, data compression presents as a promising approach to increase effective memory system capacity and also provide performance and energy advantages. This paper presents a survey of techniques for using compression in cache and main memory systems. It also classifies the techniques based on key parameters to highlight their similarities and differences. It discusses compression in CPUs and GPUs, conventional and non-volatile memory (NVM) systems, and 2D and 3D memory systems. We hope that this survey will help the researchers in gaining insight into the potential role of compression approach in memory components of future extreme-scale systems.

URLhttps://goo.gl/2okQWR
DOI10.1109/TPDS.2015.2435788