Reducing Soft-error Vulnerability of Caches using Data Compression

TitleReducing Soft-error Vulnerability of Caches using Data Compression
Publication TypeConference Paper
Year of Publication2016
AuthorsMittal, Sparsh, and Vetter Jeffrey
Conference NameACM Great Lakes Symposium on VLSI (GLSVLSI)
Conference LocationBoston, Massachusetts, USA
Keywordscache, Data compression, fault-tolerance, reliability, Resilience, Soft error, vulnerability
Abstract

With ongoing chip miniaturization and voltage scaling, particle strike-induced soft errors present increasingly severe threat to the reliability of on-chip caches. In this paper, we present a technique to reduce the vulnerability of caches to soft-errors. Our technique uses data compression to reduce the number of vulnerable data bits in the cache and performs selective duplication of more critical data-bits to provide extra protection to them. Microarchitectural simulations have shown that our technique is effective in reducing architectural vulnerability factor (AVF) of the cache and outperforms another technique. For single and dual-core system configuration, the average reduction in AVF is 5.59X and 8.44X, respectively. Also, the implementation and performance overheads of our technique are minimal and it is useful for a broad range of workloads.

DOI10.1145/2902961.2902977
Refereed DesignationRefereed