ORNL Develops an OpenACC-to-FPGA Translation Framework for High-Performance Reconfigurable Computing

13 May 2016 – A new paper entitled, "OpenACC to FPGA: A Framework for Directive-based High-Performance Reconfigurable Computing" describes how the Future Technologies Group at Oak Ridge National Laboratory (ORNL) is attacking the well-known programmability and performance portability challenges of Field Programmable Gate Arrays (FPGAs). The researchers have extended the standard, portable OpenACC specification for FPGAs and evaluated it with a prototype implementation, demonstrating that OpenACC programs can be directly compiled for FPGAs. Furthermore, the same OpenACC programs can be compiled and executed on NVIDIA and AMD graphics processors, Intel Xeon Phis, and standard x86 CPUs. Details will be presented this month in a paper at the 30th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2016).

According to co-author Jeffrey Vetter, “Reconfigurable computers, such as FPGAs, have been available for decades, and can offer more advantages in terms of performance and energy efficiency for specific workloads than other systems.” Nevertheless, FPGA devices have traditionally suffered several disadvantages that have limited their deployment in large scale HPC systems. The most significant challenges are application programmability and portability. Many projects have successfully explored the complexity of mapping source code level control and data to FPGAs. Recently, to address this issue, FPGA vendors, such as Altera and Xilinx, have introduced OpenCL as a programming system for their FPGA platforms. This new level of abstraction hides some of the complexity, while providing a new level of wide-spread portability, not offered by earlier approaches. Still, many users consider the OpenCL programming system as too low of a level of abstraction for their large, complex applications.

This new solution is built on the open-source OpenARC compiler framework from ORNL. “Using a number of existing OpenARC features, the team was able to generate Altera FPGA executables directly from the OpenACC input source code,” said co-author Seyong Lee. In addition, the researchers also evaluate the performance portability of the proposed approach using the same OpenACC applications across diverse heterogeneous architectures, including Altera FPGA, NVIDIA GPU, AMD GPU, and Intel Xeon Phi. Finally, the team shows that straightforward extensions to the OpenACC directives can provide valuable information to the compiler in terms of generating more efficient FPGA performance, such as the use of pipes and channels. Ultimately, the team plans to champion this technology for existing programming standards.

The paper (S. Lee, J. Kim, and J.S. Vetter, “OpenACC to FPGA: A Framework for Directive-based High-Performance Reconfigurable Computing”) will be presented at the 30th IEEE International Parallel and Distributed Processing Symposium in Chicago on May 25; the paper is available at DOI: http://dx.doi.org/10.1109/IPDPS.2016.28. More information about the Future Technologies Group and OpenARC system is available at http://ft.ornl.gov and http://ft.ornl.gov/research/openarc, respectively. This work was sponsored by the US Department of Energy's Office of Advanced Scientific Computing Research (ASCR).

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