|Title||Reliability Tradeoffs in Design of Volatile and Non-volatile Caches|
|Publication Type||Journal Article|
|Year of Publication||2016|
|Authors||Mittal, Sparsh, and Vetter Jeffrey|
|Journal||Journal of Circuits, Systems, and Computers|
|Keywords||last level cache, Non-volatile Memory, NVM, reliability, ReRAM, resistive RAM, Soft-error resilience, spin transfer torque RAM, STT-RAM, Write endurance|
Researchers have explored both volatile memories (e.g., SRAM and embedded DRAM) and non-volatile memories (NVMs, such as resistive RAM) for design of on-chip caches. However, both volatile and non-volatile memories present unique reliability challenges. NVMs are immune to radiation-induced soft errors, however, due to their limited write endurance, they are vulnerable to hard errors under non-uniform write distribution. By contrast, SRAM has high write endurance but is susceptible to soft errors due to cosmic radiation. SRAM-NVM hybrid caches and the management techniques for them aim to bring the best of SRAM and NVM together, however, the reliability implications of them have not been well understood. In this paper, we show that there are inherent tradeoffs in improving resilience to hard and soft errors in hybrid caches such that mitigating one may result in aggravating another. We confirm this by experiments with two recent hybrid cache management techniques. We also re-examine cache design trends in modern processors from reliability perspective. This paper provides valuable insights to system developers for making reliability-aware design decisions.