A Survey of Techniques for Designing and Managing CPU Register File

TitleA Survey of Techniques for Designing and Managing CPU Register File
Publication TypeJournal Article
Year of Publication2016
AuthorsMittal, Sparsh
JournalConcurrency and Computation: Practice and Experience
Keywordsclassification, CPU, Heterogeneous bank design, power management, processor core, Register file, Review, Soft-error resilience
Abstract

Processor register file (RF) is an important microarchitectural component used for storing operands and results of instructions. The design and operation of RF has crucial impact on the performance, energy efficiency and reliability of the processor and hence, several techniques have been recently proposed to manage RF in modern processors. In this paper, we present a survey of techniques for architecting and managing CPU register file. We classify the techniques across several parameters to underscore their similarities and differences. We hope that this paper will provide insights to researchers into working of RF and inspire even more efforts towards optimization of RF in next-generation computing systems.

URLhttps://goo.gl/HljTHh
DOI10.1109/TPDS.2016.2546249
Refereed DesignationRefereed