Future Technologies Colloquium Series

ABSTRACT:

The Cell architecture offers a huge processing power in a chip, at the expense of complexity in its use and the understanding of its behavior. The talk will describe current efforts at BSC on the development and use of programming models that should ease the portability of general applications to the Cell architecture, Cell Superscalar being the currently most advanced implementation. Cell Superscalar takes as input a sequential program annotated with directives that specify for each potentially outlined computation the input and output arguments. From it, the run time determines the actual parallelism exploitable and orchestrates the work of the different SPEs. An instrumentation framework is in place to obtain traces of the actual behavior of the chip that can then be analyzed with Paraver.