Future Technologies Colloquium Series

ABSTRACT:

The interconnect mechanisms (shared buses or crossbar) used in current chip-multiprocessors (CMP) are expected to become a bottleneck that prevents these architectures to scale to a larger number of cores. Tiled CMPs offer better scalability by integrating relatively simple cores with a lightweight point-to-point interconnect. However, the tiled CMPs proposed so far are not well suited to exploit thread-level shared-memory parallelism and the mechanisms used in current, small-scale, CMPs to support cache coherence for these applications are unlikely to be practical in a tiled CMP environment. In this talk we present two alternative mechanisms to traditional eager hardware cache coherence schemes for tiled CMPs. The first is a cost-effective hardware mechanism that forgoes hardware maintained cache coherence. The proposed mechanism is based on the key ideas that mapping of lines to physical caches is done at the page level with OS support, only so me controlled migration and replication of data is allowed, and hardware support for remote cache access. This technique allows a sufficient degree of flexibility in the mapping and is more cost-effective than previous line-based techniques that rely on broadcasts, centralized tag stores, or large redundant tag stores. The second is a scheme to enforce coherence in the software implementation of synchronization primitives, using software controlled invalidations and forced write-backs. This technique requires minimal hardware support. Experimental results show that the first scheme performs as close as 6.5%, and 24% on average, of an ideal, unrealizable, hardware coherent architecture for the SPLASH-2 benchmarks for 32 processors. Results for the second scheme show that its most conservative implementation for a single level of write-back cache shows less performance degradation than expected for the SPLASH-2 scientific and ALP multimedia benchmarks (hardware coherence takes at least 90% of the time of the software version in many cases) and that adding a shared L2 cache significantly improves the worst-case performance relative to hardware coherence, making the latter a cheap and easy to implement alternative for certain applications.

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