Future Technologies Colloquium Series


Architectural Support for Correctness and Performance Debugging


Guru Prasadh Venkataramani
Georgia Institute of Technology
May 18, 2009
10:00 AM

ORNL, Bldg. 5700, L-204

Host: Jeffrey Vetter (vetter@ornl.gov)


ABSTRACT:

Rapid advances in hardware technology have resulted in exponential growth of computing speeds and hardware platforms. Consequently, software is increasingly prone to bugs and security exploits. In order to detect these bugs, programmers need tools that continuously monitor program runtime behavior. Unfortunately, software-based tools degrade program performance by several orders of magnitude. Programmers are reluctant to use tools that are very slow. My research focuses on providing low-cost, efficient hardware solutions for memory debugging and security. In this talk, I will describe MemTracker, a novel mechanism that offers efficient and programmable hardware for memory debugging. Memory checkers usually associate state with memory words to track validity of memory access, e.g., whether load instructions access initialized heap memory, whether a return address of a function has been modified etc. MemTracker offers efficient hardware to perform such memory checks with the flexibility to implement several different memory checkers. I will discuss key design decisions along with how MemTracker can be integrated into a modern out-of-order processor. Beyond debugging for correctness, ensuring scalable performance of parallel programs for multi-core/many-core architectures is also important. Performance debugging is a key area of research that addresses scalability challenges faced by programmers. I will briefly talk about my work in this area and describe some interesting challenges that programmers will confront in the future.

BIO:

Guru Prasadh Venkataramani is a PhD candidate in the School of Computer Science at Georgia Institute of Technology where he is advised by Prof. Milos Prvulovic. Guru’s research area is computer architecture with emphasis on providing efficient and low-cost hardware support for software debugging, security and programmability. He is also interested in hardware solutions for performance tuning especially for multi-core and emerging many-core architectures. He is a member of IEEE and ACM.

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