wiki:WikiStart

Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

The Blackcomb effort seeks to create and understand new memory technologies, develop their roles in exascale systems, adapt applications to them, and assess their relative merits. We focus on emerging nonvolative memory (NVM) technologies, including spin-torque-transfer RAM (STT-RAM), phase-change RAM (PC-RAM), and memristor (resistive RAM, or R-RAM).

See our most recent one page description at https://ft.ornl.gov/trac/blackcomb/attachment/wiki/WikiStart/blackcomb-one-pager.2.pdf

Participants

  • Oak Ridge National Laboratory
  • Hewlett Packard Laboratories
  • University of Michigan, Ann Arbor
  • Penn State

Blackcomb is sponsored by the DOE Office of Science's Advanced Scientific Computing Office.

Objectives

Rearchitect servers and clusters, using nonvolatile memory (NVM) to overcome resilience, energy, and performance walls in exascale computing:

  • Ultrafast checkpointing to nearby NVM
  • Redesign the memory hierarchy for exascale, using new memory technologies
  • Replace disk with fast, low-power NVM
  • Enhance resilience and energy efficiency
  • Provide added memory capacity

Open-source Tool Released

  • DESTINY (a 3D dEsign-Space exploraTIon tool for SRAM, eDRAM and Non-volatile memorY)

Code, Relevant paper, extended technical report, manual and tool review

Recent Publications

The download links for most publications are available here.

  • S. Mittal, J. Vetter, "Reducing Soft-error Vulnerability of Caches using Data Compression", ACM Great Lakes Symposium on VLSI (GLSVLSI), 2016.
  • S. Mittal, J. Vetter, "A Technique For Improving Lifetime of Non-volatile Caches using Write-minimization", MDPI Journal of Low Power Electronics and Applications (Special issue on Energy-efficient and Scalable Embedded Memories for Future Technologies), 2016.
  • S. Mittal, "A Survey of Techniques for Architecting and Managing GPU Register File", IEEE Transactions on Parallel and Distributed Systems (TPDS), 2016.
  • S. Mittal, "A Survey of Techniques for Architecting Processor Components using Domain Wall Memory", in ACM JETC, 2017
  • S. Mittal, "A Survey of Techniques for Designing and Managing CPU Register File", Concurrency and Computation: Practice and Experience, 2016.
  • S. Mittal, J. Vetter, "Reliability Tradeoffs in Design of Volatile and Non-volatile Caches", Journal of Circuits, Systems, and Computers, 2016
  • S. Mittal, "A Survey Of Techniques for Approximate Computing", ACM Computing Surveys, 2016.
  • S. Mittal, "A Survey of Recent Prefetching Techniques for Processor Caches", ACM Computing Surveys, 2016.
  • P. Wu, D. Li, Z. Chen, J. Vetter, S. Mittal, "Algorithm-Directed Data Placement in Explicitly Managed Non-volatile Memory", ACM International Symposium on High-Performance Parallel and Distributed Computing (HPDC), 2016
  • S. Mittal and J.S. Vetter, "A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems", in IEEE Trans. on Parallel and Distributed Systems (TPDS), 2016
  • S. Mittal and J.S. Vetter, "A Survey Of Techniques for Architecting DRAM Caches", in IEEE TPDS, 2015
  • S. Mittal and J Vetter, "A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems", IEEE Trans. on Parallel and Distributed Systems (TPDS), 2016
  • S. Mittal, J. Vetter, "A Technique For Improving Lifetime of Non-volatile Caches using Write-minimization", MDPI Journal of Low Power Electronics and Applications (Special issue on Energy-efficient and Scalable Embedded Memories for Future Technologies), vol. 6, issue 1, 2016.
  • S. Mittal, "A Survey of Cache Bypassing Techniques", MDPI Journal of Low Power Electronics and Applications (Special issue on Energy-efficient and Scalable Embedded Memories for Future Technologies), 2016.
  • S. Mittal and J Vetter, "A Survey of CPU-GPU Heterogeneous Computing Techniques", ACM Computing Surveys, 2015
  • S. Mittal and J Vetter, "A Survey of Techniques for Modeling and Improving Reliability of Computing Systems", IEEE Trans. on Parallel and Distributed Systems (TPDS), 2016
  • S. Mittal, "A Survey Of Architectural Techniques for Managing Process Variation", ACM Computing Surveys, 2016
  • S. Mittal, "A Survey Of Techniques for Architecting and Managing Asymmetric Multicore Processors", ACM Computing Surveys, 2016
  • S. Mittal, "A Survey Of Techniques for Cache Locking", ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016
  • S. Mittal, J. S. Vetter, "Equalwrites: Reducing Intra-set Write Variations for Enhancing Lifetime of Non-volatile Caches", IEEE Transactions on VLSI Systems, 2015.
  • J. S. Vetter, S. Mittal, "Opportunities for Nonvolatile Memory Systems in Extreme-Scale High Performance Computing", Computing in Science and Engineering special issue, 2015.
  • C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, Tao Zhang, S. Yu, Y. Xie “Overcoming the Challenges of Cross-Point Resistive Memory Architectures.” Proceedings of the 21st IEEE Intl. Symp. on High Performance Computer Architecture (HPCA). 2015.
  • S. Mittal, J.S. Vetter, "A Survey of Methods for Analyzing and Improving GPU Energy Efficiency", ACM Computing Surveys (CSUR), 2015.
  • K. Ma, Yang Zheng, S. Li, Karthik Swaminathan, Xueqing Li, Yougpan Liu, Jack Sampson, Y. Xie, Vijay Narayanan “Architecture Exploration for Ambient Energy Harvesting Nonvolatile Processors.” Proceedings of the 21st IEEE Intl. Symp. on High Performance Computer Architecture (HPCA). 2015.
  • S. Mittal, "A Survey Of Architectural Techniques for Near-Threshold Computing", in ACM JETC, 2016
  • M. Poremba, Tao Zhang, Y. Xie, “NVmain 2.0: Non-volatile memory simulator”, Computer Architecture Letter, 2015.
  • S. Mittal, J. Vetter, "ENLIVE: A Write-minimization Technique For Improving the Lifetime of Non-volatile Caches", ORNL, USA, technical report, ORNL/TM-2015/232, 2015.
  • S. Mittal, M. Poremba, J. S. Vetter, Y. Xie, "Exploring Design Space of 3D NVM and eDRAM Caches Using DESTINY Tool", Oak Ridge National Laboratory, USA, technical report ORNL/TM-2014/636, 2014.
  • M. Poremba, S. Mittal, D. Li, J. S. Vetter and Y. Xie, "DESTINY: A Tool for Modeling Emerging 3D NVM and eDRAM caches", in Design Automation and Test in Europe (DATE), 2015
  • S. Mittal, "A Survey of Power Management Techniques for Phase Change Memory", accepted in International Journal of Computer Aided Engineering and Technology (IJCAET), 2014.
  • S. Mittal and J.S. Vetter. "AYUSH: A Technique for Extending Lifetime of SRAM-NVM Hybrid Caches", IEEE Computer Architecture Letters (CAL), 2014
  • S. Mittal and J. Vetter, "AYUSH: Extending Lifetime of SRAM-NVM Way-based Hybrid Caches Using Wear-leveling", IEEE MASCOTS 2015
  • S. Mittal and J.S. Vetter. "Equalchance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches", USENIX Workshop on Interactions of NVM/Flash with Operating Systems and Workloads (INFLOW), 2014
  • S. Mittal, J.S. Vetter and D. Li. "WriteSmoothing:Improving Lifetime of Non-volatile Caches Using Intra-set Wear-Leveling". In 24th ACM International Conference on Great Lakes Symposium on VLSI, 2014
  • S. Mittal, J.S. Vetter and D. Li. "Improving Energy Efficiency of Embedded DRAM Caches for High-end Computing Systems". In 23rd ACM International Symposium on High Performance Parallel and Distributed Computing, 2014
  • S. Mittal, J.S.Vetter and D. Li, "LastingNVCache: A Technique for Improving the Lifetime of Non-volatile Caches", in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014.
  • S. Mittal, J. S. Vetter, "Addressing Inter-set Write-Variation for Improving Lifetime of Non-Volatile Caches", In 5th Annual Non-Volatile Memories Workshop University of California, San Diego, 2014.
  • S. Mittal, "A Survey of Architectural Techniques For Improving Cache Power Efficiency", in Elsevier Sustainable Computing: Informatics and Systems (SUSCOM), vol. 4, no. 1, pp. 33-43, 2014.
  • S. Mittal, "A Survey Of Techniques for Managing and Leveraging Caches in GPUs", Journal of Circuits, Systems and Computers (JCSC), 2014.
  • S. Mittal, Z. Zhang, J. S. Vetter, "Flexiway: A Cache Energy Saving Technique Using Fine-grained Cache Reconfiguration", In 31st IEEE International Conference on Computer Design (ICCD), 2013.
  • S. Mittal, J.S. Vetter and D. Li, "A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches", in IEEE Transactions on Parallel and Distributed Systems (TPDS) 2014.
  • Tao Zhang, Ke Chen, Cong Xu, Guangyu Sun, Tao Wang, Yuan Xie "Half-DRAM: a High-bandwidth and Low-power DRAM System from the Rethinking of Fine-grained Activation" To appear in proceedings of the 41st International Symposium on Computer Architecture (ISCA),2014.
  • S. Li, A. Li, Yongpan Liu, Y. Xie, Huazhong Yang “Nonvolatile Memory Allocation and Hierarchy Optimization for High-Level Synthesis.” Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2015.
  • Jue Wang, X. Dong, Y. Xie. “Preventing STT-RAM Last-Level Caches from Port Obstruction.” ACM Transactions on Architecture and Code Optimization (TACO), 2014.
  • Z. Wang, S. Shan, Ting Cao, Junli Gu, Yi Xu, Y. Xie, D. Jimenez. “WADE: Writeback-Aware Dynamic Cache Management for NVM-based Main Memory System.” ACM Transactions on Architecture and Code Optimization (TACO), 2014.
  • W. Wen, Y. Zhang, Yiran Chen, Yu Wang, Y. Xie . “PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy? Analysis Method” IEEE Transactions on Computer Aids Design (TCAD)., pp.1644-1656, Vol. 33, No. 11, Nov. 2014.
  • Jue Wang, X. Dong, Y. Xie, “Enabling High-Performance LPDDRx-Compatible MRAM”, TACO , 2014.
  • Yang Zheng, C. Xu, Y. Xie “Modeling Framework for Cross-point Resistive Memory Design Emphasizing Reliability and Variability Issues.” Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2015.
  • J. Zhao, Onur Multu, Y. Xie “FIRM: Fair and High-performance Memory Scheduling for Persistent Memory Systems” To appear in Proceedings of IEEE/ACM International Conference on Microarchitecture (MICRO), 2014.
  • Ping Chi, C. Xu, Tao Zhang, X. Dong, Y. Xie ” Proceedings of the 33rd International Conference on Computer-Aided Design (ICCAD),2014. IEEE/ACM William J. Mccalla ICCAD Best Paper Award.
  • C. Xu, Pai-Yu Chen, D. Niu, Yang Zheng, S. Yu, Y. Xie “Architecting 3D Vertical Resistive Memory for Next-Generation Storage Systems” Proceedings of the 33rd International Conference on Computer-Aided Design (ICCAD),2014.
  • Tao Zhang, Ke Chen, G. Sun, and Y. Xie. “3D-SWIFT: A High-Performance 3D-Stacked Wide IO DRAM.” To appear in Proceedings of The 24th Great Lake Symposium on VLSI (GLSVLSI) , 2014. Best paper award nomination
  • C. Xu, D. Niu, Yang Zheng, S. Yu and Y. Xie. “Reliability-Aware Cross-Point Resistive Memory Design.” To appear in Proceedings of The 24th Great Lake Symposium on VLSI (GLSVLSI) , 2014.
  • Tao Zhang, C. Xu, G. Sun, Y. Xie. “CREAM: A Concurrent-Refresh-Aware DRAM Memory System.” Proceedings of The 20th IEEE International Symposium On High Performance Computer Architecture (HPCA) , 2014.
  • Zhe Wang, D. Jimenez, C. Xu, G. Sun, Y. Xie. “Adaptive Placement and Migration Policy for an STT-RAM-Based Hybrid Cache.” Proceedings of The 20th IEEE International Symposium On High Performance Computer Architecture (HPCA) , 2014.
  • C. Xu, D. Niu, S. Yu, Y. Xie “Modeling and Design Analysis of 3D Vertical Resistive Memory - A Low Cost Cross-Point Architecture.” Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2014.
  • D. Li, Z. Chen, P. Wu, J.S. Vetter. “Rethinking Algorithm-Based Fault Tolerance with a Cooperative Software-Hardware Approach". In 25th ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis, 2013
  • B. Wang, B. Wu, D. Li, X. Shen, W. Yu, Y. Jiao and J.S. Vetter. "Exploring Hybrid Memory for GPU Energy Efficiency through Software-Hardware Co-Design ". In 22nd ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques, 2013
  • B. Wang, Y. Jiao, W. Yu, X. Shen, D. Li and J.S. Vetter. "A Versatile Performance and Energy Simulation Tool for Composite GPU Global Memory". In 21st IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 2013
  • B. Wang, B. Wu, D. Li, X. Shen, W. Yu, Y. Jiao, and J.S. Vetter, “Exploring Hybrid Memory for GPU Energy Efficiency through Software-Hardware Co-Design,” in International Conference Parallel Architectures and Compilation Techniques (PACT). Edinburgh, Scotland: IEEE/ACM, 2013.
  • Jue Wang, Xiangyu Dong, and Yuan Xie. OAP: An obstruction-aware cache management policy for STT-RAM last-level caches, ACM/IEEE International Conference on Design Automation and Test in Europe (DATE), 2013, Best Paper Candidate.
  • D. Yoon, J. Chang, R. Schreiber, N. Jouppi. Practical nonvolatile multilevel-cell phase change memory. SC 13, Nov. 2013
  • B. Giridhar, M. Cieslak, D. Duggal, R. Dreslinski, H. Chen, R. Patti, B. Hold, C. Chakrabarti, T. Mudge, D. Blaauw, Exploring DRAM organizations for energy-efficient and resilient exascale memories. SC 13, Nov. 2013.
  • Jishen Zhao, Sheng Li, Doe Hyun Yoon, Norm Jouppi, Yuan Xie. "Kiln: Closing the Performance Gap Between Systems With and Without Persistence Support." Proceedings of IEEE/ACM International Conference on Microarchitecture (MICRO), 2013. Best Paper Honorable Mention.
  • Dimin Niu, Cong Xu, Naveen Muralimanoha, Norm Jouppi, Yuan Xie. "Design of Cross-point Metal-oxide ReRAM Em-phasizing Reliability and Cost." Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2013.
  • Dimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie. "Low Power Multi-Level-Cell Resistive Memory Design with Incomplete Data Mapping" Proceedings of ACM/IEEE International Conference on Computer Design (ICCD), 2013.
  • Cong Xu, Dimin Niu, Naveen Muralimanohar, Yuan Xie, "Understanding the Trade-offs in Multi-Level Cell ReRAM Memory Design" Proceedings of ACM/IEEE Design Automation Conference (DAC), 2013.
  • Xiangyu Dong, Norm Jouppi, Yuan Xie. "A Circuit-Architecture Co-optimization Framework for Exploring Non-volatile Memory Hierarchies." ACM Transactions on Architecture and Code Optimization (TACO), Vol. 10, No. 4, 12/2013
  • Jishen Zhao, Guangyu Sun, Gabriel Loh, Yuan Xie. "Optimizing GPU Energy Efficiency with In-Package Graphics Memory and Recon gurable Memory Interface." ACM Transactions on Architecture and Code Optimization (TACO), Vol. 10, No. 4, 12/2013
  • J. Zhao, Sheng Li, Doe Hyun Yoon, Norm Jouppi, Y. Xie. “Kiln: Closing the Performance Gap Between Systems With and Without Persistence Support.” Proceedings of IEEE/ACM International Conference on Microarchitecture (MICRO), 2013. Best Paper Honorable Mention.
  • D. Niu, C. Xu, N. Muralimanoha, Norm Jouppi, Y. Xie. “Design of Cross-point Metal-oxide ReRAM Em- phasizing Reliability and Cost.” Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2013
  • D. Niu, Qiaosha Zou, C. Xu, Y. Xie. “Low Power Multi-Level-Cell Resistive Memory Design with Incomplete Data Mapping” Proceedings of ACM/IEEE International Conference on Computer Design (ICCD), 2013.
  • C. Xu, D. Niu, N. Muralimanohar, Y. Xie, “Understanding the Trade-offs in Multi-Level Cell ReRAM Memory Design” Proceedings of ACM/IEEE Design Automation Conference (DAC), 2013.
  • Jue Wang, X. Dong, and Y. Xie “OAP: An Obstruction-Aware Cache Management Policy for STT-RAM Last-Level Caches” Proceedings of ACM/IEEE International Conference on Design Automation and Test in Europe (DATE), 2013, Best Paper Candidate .
  • Jue Wang, X. Dong, Norm Jouppi, and Y. Xie “i2WAP: Improving Non-Volatile Cache Lifetime by Reduc- ing Inter- and Intra-Set Write Variations” Proceedings of IEEE International Symposium on High- Performance Computer Arhitecture Conference (HPCA), 2013, pp.234-245.,
  • Y. Xie, “Emerging Memory Technologies: Design, Architecture, and Applications.” Springer. 2013
  • X. Dong, Norm Jouppi, Y. Xie. “A Circuit-Architecture Co-optimization Framework for Exploring Non-volatile Memory Hierarchies.” ACM Transactions on Architecture and Code Optimization (TACO), Vol. 10, No. 4, 12/2013.
  • D. Li, J.S. Vetter, G. Marin, C. Mccurday, C. Cira, Z. Liu, and W. Yu, “Identifying Opportunities for Byte-Addressable Non-Volatile Memory in Extreme-Scale Scientific Applications,” in IEEE IPDPS. Shanghai: IEEEE, 2012.
  • D. Li, J.S. Vetter, and W. Yu, “Classifying Soft Error Vulnerabilities in Extreme-Scale Scientific Applications Using a Binary Instrumentation Tool,” in SC12: 2012..
  • J. Zhao and Y. Xie “Optimizing Bandwidth and Power of Graphics Memory with Hybrid Memory Technologies and Adaptive Data Migration” Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012,
  • M. Poremba and Y. Xie “NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories” Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2012, pp.392-397.
  • D. Niu, C. Xu, N. Muralimanohar, Norman P. Jouppi, Y. Xie “Design Trade-Offs for High Density Cross- Point Resistive Memory ” Proceedings of ACM/IEEE International Symposium on Low Power Electronic Design (ISLPED), 2012, pp.209-214.,
  • X. Dong, C. Xu, Y. Xie, Norm Jouppi. “NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Non-Volatile Memory” IEEE Transactions on Computer Aids Design (TCAD)., pp.994 - 1007, Vol.31 , No.7, July, 2012.
  • Adwait Jog, Asit Mishra, C. Xu, Y. Xie, Vijaykrishnan Narayanan, Chita Das, Ravi Iyer “Cache Revive: Architecting Volatile STT-RAM Caches for Enhanced Performance ” Proceedings of ACM/IEEE Design Automation Conference (DAC), 2012, pp.243-252.
  • Jue Wang, X. Dong, Y. Xie “Point and Discard: A Hard-Error-Tolerant Architecture for Non-Volatile Last Level Caches ” Proceedings of ACM/IEEE Design Automation Conference (DAC), 2012, pp. 253-258.
  • W. Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Y. Xie “PS3-RAM: A Fast, Portable and Scalable Statistical STT-RAM Reliability Analysis Method ” To appear in Proceedings of ACM/IEEE Design Automation Conference (DAC), 2012, pp. 1187-1192.
  • D. Niu, Yang Xiao, Y. Xie “Low Power Memristor-Based ReRAM Design with Error Correcting Code”, Pro- ceedings of ACM/IEEE Asia and South-Pacific Design Automation Conference, 2012.
  • D. Yoon, J. Chang, N. Muralimanohar, and P. Ranganathan. BOOM: Enabling mobile memory based low-power server DIMMs, 39th International Symposium on Computer Architecture (ISCA-39), June 2012
  • J. Zhao, C. Xu, Y. Xie “Bandwidth-Aware Reconfigurable Cache Design with Hybrid Memory Technologies”, Proceedings of ACM/IEEE Intl. Conf. on Computer-aided Design (ICCAD), 2011, pp. 48-55.
  • C. Xu, D. Niu, Xiaochun Zhu, Seung H. Kang, M. Nowak and Y. Xie “Device-Architecture Co-Optimization of STT-RAM Based Memory for Low Power Embedded System”, Proceedings of ACM/IEEE Intl. Conf. on Computer-aided Design (ICCAD), 2011, pp.463-470.
  • G. Sun, Eren Kursun, Jude Rivers, Y. Xie “Improving the Vulnerability of CMPs to Soft Erros with 3D Stacked Non-volatile Memory”, Proceedings of ACM/IEEE Intl. Conf. on Computer Design (ICCD), 2011, pp. 366-372.
  • Jue Wang, X. Dong, Guanyu Sun, D. Niu and Y. Xie. “Energy-Efficient Multi-Level Cell Phase-Change Memory System with Data Encoding”, To appear in Proceedings of ACM/IEEE Intl. Conf. on Computer Design (ICCD), 2011, pp.175-182.
  • A. Mishra, X. Dong, G. Sun, Y. Xie, N. Vijaykrishnan, C. Das “Architecting Nocs for Stacked 3D STT-RAM Caches in CMPs”, Proceedings of ACM/IEEE International Conference on Computer Architecture (ISCA), 2011, pp.69-80,
  • G. Sun, C. Hughes, C. Kim, J. Zhao, C. Xu, Y. Xie, Yen-Kuanchen “Moguls: a Model to Explore Memory Hierarchy for Throughput Computing”, Proceedings of ACM/IEEE International Conference on Computer Architecture (ISCA), 2011, pp.377-388.
  • X. Dong, Y. Xie, N. Muralimanohar, Norm Jouppi. “Hybrid Checkpointing using Emerging Non-Volatile Memories for Future Exascale Systems.” ACM Transactions on Architecture and Code Optimization (TACO), Vol.8, No. 2, Article 5, 29 pages, July 2011
  • C. Xu, X. Dong, Norm Jouppi, and Y. Xie “Design Implications of Memristor-Based RRAM Cross-Point Structures”, In Proceedings of ACM/IEEE Design Automation and Test in Europe Conference (DATE), pp.734-739, 2011

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