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The Ninth Workshop
on
High-Performance, Power-Aware
Computing
May 20, 2013, Boston, Massachusetts
USA
 
The 9th Workshop on High-Performance,
Power-Aware Computing (HPPAC 2013) will be held on May 20, 2013 in Boston, USA, in conjunction with the
27th Annual International Parallel & Distributed
Processing Symposium (IPDPS 2013), to be
held on May 20-24, 2013, Boston, USA.
Scope
High-performance computing is and has always been
performance-oriented. However, a consequence of the push towards
maximum performance is increased energy consumption, especially in
datacenters and supercomputing centers. Moreover, as peak
performance is rarely attained, some of this energy consumption
results in little or no performance gain. In addition, large energy
consumption costs datacenters and supercomputing centers a
significant amount of money and wastes natural resources.
The main goal of this workshop is to provide a timely forum for
the exchange and dissemination of new ideas, techniques, and
research in high-performance, power-aware computing (HPPAC). HPPAC
will present research that reduces (1) power consumption, (2) energy
consumption, or (3) heat generation with little or no performance
penalty in high-performance computing systems. In effect, the
workshop aims to move towards "greener" solutions for datacenters
and supercomputing centers. Examples include Green Destiny (2001), The Green Grid (2007), The Green500 List (2007), and
the INRIA
Green-Net Initiative (2008).
Submission Guidelines
All papers should not exceed 8 single-spaced, double column
pages (US Letter) in 10pt font. All papers will be reviewed.
Accepted papers will appear in the printed program book and CD-ROM
proceedings of the main conference, IPDPS2013. Click here to submit a paper.
Program
| 8:30 |
Opening Remarks |
| 9.00-10.00 |
Keynote: Tali Moreshet (Chair: Bronis R. de
Supinski) |
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Energy-Efficient Synchronization and
Parallelism
Computing systems from supercomputers to embedded systems
are turning to multi-core and many-core architectures for the
purpose of improved performance per Watt. Thus, in order
to extract performance, programmers need to expose a high
degree of parallelism. Because these systems often rely
on a shared-memory abstraction, this requires providing
efficient, energy-effective, and convenient mechanisms for
synchronization and communication. This talk will
overview a range of energy-efficient synchronization
mechanisms, including locks, barriers, and transactional
memory. |
| 10.00-10.30 |
Coffee break |
| 10.30-12.00 |
Session 1 (Chair: Tali Moreshet): Power Efficient
Hardware |
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Measuring Power Consumption on IBM Blue
Gene/Q |
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Sean Wallace, Venkatram Vishwanath, Susan Coghlan, Zhiling
Lan, and Michael E. Papka |
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PowerTune: Differentiated Power Allocation in
Over-provisioned Multicore Systems |
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Vishal Gupta and Karsten Schwan |
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Decreasing Network Power with On-Off Links
Informed by Scientific Applications |
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Gilbert Hendry |
| 12.00-1.00 |
Lunch |
| 1.00-2.30 |
Session 2 (Chair: Dong Li): Energy/Power Measurement and
Profiling |
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Design of a Concentrated Torus Topology with
Channel Buffers and Efficient Crossbars in NoCs |
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Dominic DiTomasoy, Randy Morrisy, Evan Jolley, Ashwini
Sarathyz, Ahmed Louriz, and Avinash Kodi |
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Power Measurement and Concurrency Throttling for
Energy Reduction in OpenMP Programs |
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Allan K. Porterfield, Stephen L. Olivier, Sridutt
Bhalachandra and Jan F. Prins |
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General Recommendations for High Performance
Computing Data Center Energy Management Dashboard
Display |
|
Dale Sartor, Rod Mahdavi, Ben D. Radhakrishnan, Anna Maria
Bailey, Ralph Wescott, and Natalie Bates |
| 2.30-3.00 |
Coffee break |
| 3.00-4.30 |
Session 3(Chair: Susan Coghlan): Large Scale Power
Management |
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Energy Consumption Models and Predictions
for Large-scale Systems |
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Taghrid Samak, Christine Moriny and David Bailey |
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Analysis of a Self-Organizing Algorithm for Energy
Saving in Data Centers |
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Carlo Mastroianni, Michela Meo and Giuseppe Papuzzo |
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Toward Runtime Power Management of Exascale
Networks by On/Off Control of Links |
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Ehsan Totoni, Nikhil Jain and Laxmikant V. Kale |
| 4.30-6.00 |
Session 4 (Chair: Martin Schulz): Compiler and Runtime Techniques |
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A Compiler Analysis to Determine Useful Cache Size
for Energy Efficiency |
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Sanket Tavarageri and P. Sadayappan |
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Energy-efficient Sparse Matrix Autotuning with CSX
- A Trade-off Study |
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Jan Christian Meyer, Juan Manuel Cebrian, Lasse Natvig,
Vasileios Karakasis, Dimitris Siakavaras, and Konstantinos
Nikas |
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Evaluation of Energy Characteristics of MPI
Communication Primitives with RAPL |
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Akshay Venkatesh, Krishna Kandalla and Dhabaleswar K.
Panda |
| 6.00 |
Final Remarks | |
- Kevin Barker, Pacific Northwest National Laboratory
- Lloyd Bircher, AMD
- Patrick Bridges, University of New Mexico
- Laura Carrington, San Diego Supercomputer Center
- Wuchun Feng, Virginia Tech
- Canturk Isci, IBM
- Rong Ge, Marquette University
- Roberto Gioiosa, Pacific Northwest National Laboratory
- Rob Knauerhase, Intel Labs
- Zhiling Lan, Illinois Institute of Technology
- Laurent Lefevre, INRIA and University of Lyon
- David Lowenthal, University of Arizona
- Naoya Maruyama, RIKEN Advanced Institute for Computational Science
- Tali Moreshet, Swarthmore College
- M. Mustafa Rafique, IBM Research Dublin
- Suzanne Rivoire, Sonoma State University
- Barry Rountree, Lawrence Livermore National Laboratory
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