Postdoctoral Research Associate in Emerging Architectures for HPC
Email: mittals at ornl dot gov
Overall area: Computer architecture (CPU, GPU and CPU-GPU heterogeneous systems), High-performance computing
Specific research interests: architectural simulation, energy-efficient and reliable main memory and cache design, sustainable computing, low-power computing, cache reconfiguration.
Memory technologies: SRAM, non-volatile memory (NVM) devices (STT-RAM, PCM, ReRAM), DRAM memory and eDRAM cache
Awards and Honors
1. My research has been covered by several technical news websites, e.g. Phys.org, InsideHPC 1, InsideHPC 2, InsideHPC 3, Primeur Magazine, StorageSearch, Data-Compression.info, TechEnablement, ScientificComputing, SemiEngineering (semiconductor engineering), ReRAM forum and HPCWire.
2. Received Distinguished Contribution rating at ORNL based on 2013-2014 performance appraisal. This rating recognizes the top 10 percent of staff.
3. Received Outstanding Contribution rating at ORNL based on 2014-2015 performance appraisal. Also received a performance award.
4. ECpE fellowship from Electrical and Computer Engineering Department, Iowa State University, USA of $2500 in 2008.
5. Peer Research Award from Iowa State University, USA of $200 in 2013.
6. Topper in Electronics batch of year 2008 in ECE department at IIT Roorkee and received Institute Silver Medal for this.
7. Institute Silver Medal for Best B.Tech project award in Electronics and Computer Engineering (ECE) Department at IIT Roorkee.
8. Sumer Chand Jain Scholarship of INR 10,000 from IIT Roorkee.
9. Best Student Award from High School (named MHS, Jaipur, Rajasthan, India) in 2004.
1. ACM HPDC 2014 (acceptance rate ~ 16%): Improving energy efficiency of Embedded DRAM Caches for High-end Computing Systems
2. ACM/IEEE Supercomputing 2014 (acceptance rate 21% Best Student Paper Session): Quantitatively Modeling Application Resiliency with the Data Vulnerability Factor
3. IEEE ICCD 2013 (acceptance rate ~ 25%): FlexiWay: A Cache Energy Saving Technique Using Fine-grained Cache Reconfiguration
4. IEEE Trans. on VLSI 2015 (impact factor 1.14): EqualWrites: Reducing Intra-set Write Variations for Enhancing Lifetime of Non-volatile Caches
5. IEEE Trans. on VLSI 2013 (impact factor 1.14): MASTER: A Multicore Cache Energy Saving Technique Using Dynamic Cache Reconfiguration
On big.LITTLE-style asymmetric multicore processors (for example, Samsung's Exynos 5 Octa)
On techniques for approximate computing and storage
On comparison between energy efficiency of GPUs, FPGAs and CPUs
On architectural techniques for improving reliability in CPUs and GPUs (soft-error resilience and redundancy schemes)
On architectural techniques for managing process variation in CPUs and GPUs
On architectural techniques for stacked-DRAM caches, eDRAM and NVM caches, NVMs (e.g. Flash) for storage systems and main memory
On architectural techniques for cache locking
On question answering systems (natural language processing)
See http://publicationslist.org/sparsh0mittal for full publication list and download links.
The PowerPoint slides of a few conference presentations are available here.
1. DESTINY: DESTINY is an acronym for 3D design-space exploration tool for SRAM, eDRAM and non-volatile memory. It is a tool for modeling both 2D and 3D caches designed with five prominent memory technologies: SRAM, eDRAM, PCM, STT-RAM and ReRAM, which covers both conventional and emerging technologies. In its purpose, it is similar to CACTI, CACTI-3DD or NVSim. (Source-code, manual, DATE 2015 paper and extended technical report.). See its news coverage on ReRAM forum. Join DESTINY mailing list or see archive of previous conversations.
The proverb goes, write your own destiny. Hence, we have written our own [tool named] DESTINY. J
2. Both serial and parallel versions of code of red-black SOR (successive over-relaxation) method in three state-of-the-art languages, viz. Chapel (from Cray Inc.), D (also called dlang, from Digital Mars) and Go (also called golang, from Google) can be downloaded for academic use from this link. They were used in this paper. Chapel version of the code has been incorporated in Chapel performance test suite/examples.
PhD from Iowa State University (ISU), Ames, Iowa, USA (2008-2013).
BTech from Indian Institute of Technology (IIT) Roorkee, Uttarakhand, India (2004-2008).
ACM: Computing Surveys (2 times), TACO (2 times)
IEEE: CAL (3 times), Intelligent Systems, ISVLSI, JETCAS, Trans. on Computers (TC), TCAD, HiPC student research symposium
Springer: Cluster Computing, J. of Supercomputing, Springer book High Performance Computing in Power and Energy Systems
IET CDT, MDPI Sustainability, Concurrency and Computation,
Matthew (Matt) Poremba, Penn State University, USA, 2014/06-2014/09
1. University of Michigan, 2015/11
2. New York University 2016/02
Programming Languages/tools: C, C++, CUDA, Go (from Google), X10 (from IBM), Matlab, Simulink, System Generator (Xilinx), python, LaTeX, Gnuplot.
Architectural Simulators: Simplescalar, GEMS, Gem5, Sniper, MARSS, GPGPUSim.
1 Bethel Valley Road
Building 5100, Room 229, MS-6173
Oak Ridge, TN, USA 37831-6173