Postdoctoral Research Associate in Emerging Architectures for HPC
Email: mittals at ornl dot gov
July 2015: An internship position for PhD students is available at Future Technologies Group (ORNL) for research in Computer Architecture related area. Interested students may send resume at mittals at ornl dot gov.
Overall area: Computer architecture (CPU, GPU and CPU-GPU heterogeneous systems), High-performance computing
Specific research interests: architectural simulation, energy-efficient main memory and cache design, sustainable computing, low-power computing, cache reconfiguration.
Memory technologies: SRAM, non-volatile memory (NVM) devices (STT-RAM, PCM, ReRAM), DRAM memory and eDRAM cache
Research objectives: Improving performance, energy efficiency and resilience/reliability of cache and memory systems. Improving lifetime of NVM devices.
3. IEEE Trans. on VLSI 2013 (impact factor 1.14): MASTER: A Multicore Cache Energy Saving Technique Using Dynamic Cache Reconfiguration
4. IEEE TPDS 2015 (impact factor 2.17): A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems (See its news coverage on StorageSearch website)
5. IEEE TPDS 2015 (impact factor 2.17): A Survey of Techniques for Modeling and Improving Reliability of Computing Systems
6. IEEE TPDS 2015 (impact factor 2.17): A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems
7. IEEE TPDS 2015 (impact factor 2.17): A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches
8. IEEE TPDS 2015 (impact factor 2.17): A Survey Of Techniques for Architecting DRAM Caches
9. ACM/IEEE Supercomputing 2014 (acceptance rate 21% Best Student Paper Session): Quantitatively Modeling Application Resiliency with the Data Vulnerability Factor
10. IEEE ICCD 2013 (acceptance rate ~ 25%): FlexiWay: A Cache Energy Saving Technique Using Fine-grained Cache Reconfiguration
11. ACM HPDC 2014 (acceptance rate ~ 16%): Improving energy efficiency of Embedded DRAM Caches for High-end Computing Systems
12. IEEE Trans. on VLSI 2015 (impact factor 1.14): EqualWrites: Reducing Intra-set Write Variations for Enhancing Lifetime of Non-volatile Caches
13. JCSC 2014 (impact factor 0.33): A Survey Of Techniques for Managing and Leveraging Caches in GPUs
14. Elsevier SUSCOM 2014: A Survey of Architectural Techniques For Improving Cache Power Efficiency
See http://publicationslist.org/sparsh0mittal for full publication list and download links.
The PowerPoint slides of a few conference presentations are available here.
1. DESTINY: DESTINY is an acronym for 3D design-space exploration tool for SRAM, eDRAM and non-volatile memory. It is a tool for modeling both 2D and 3D caches designed with five prominent memory technologies: SRAM, eDRAM, PCM, STT-RAM and ReRAM, which covers both conventional and emerging technologies. In its purpose, it is similar to CACTI, CACTI-3DD or NVSim. (Source-code, manual, DATE 2015 paper and extended technical report.). See its news coverage on ReRAM forum.
The proverb goes, write your own destiny. Hence, we have written our own [tool named] DESTINY. J
2. Both serial and parallel versions of code of red-black SOR (successive over-relaxation) method in three state-of-the-art languages, viz. Chapel (from Cray Inc.), D (also called dlang, from Digital Mars) and Go (also called golang, from Google) can be downloaded for academic use from this link. They were used in this paper. Chapel version of the code has been incorporated in Chapel performance test suite/examples.
PhD from Iowa State University (ISU), Ames, Iowa, USA (2008-2013).
BTech from Indian Institute of Technology (IIT) Roorkee, Uttarakhand, India (2004-2008).
Awards and Honors
1. Received Distinguished Contribution rating at ORNL based on 2013-2014 performance appraisal. This rating recognizes the top 10 percent of staff.
2. ECpE fellowship from Electrical and Computer Engineering Department, Iowa State University, USA of $2500 in 2008.
3. Peer Research Award from Iowa State University, USA of $200 in 2013.
4. Topper in Electronics batch of year 2008 in ECE department at IIT Roorkee and received Institute Silver Medal for this.
5. Institute Silver Medal for Best B.Tech project award in Electronics and Computer Engineering (ECE) Department at IIT Roorkee.
6. Sumer Chand Jain Scholarship of INR 10,000 from IIT Roorkee.
7. Best Student Award from High School (named MHS, Jaipur, Rajasthan, India) in 2004.
Reviewer for: ACM Computing Surveys (2 times), ACM TACO, IEEE Intelligent Systems, IEEE ISVLSI, IEEE JETCAS, IEEE CAL, Springer Cluster Computing, Springer J. of Supercomputing, Springer book High Performance Computing in Power and Energy Systems.
Matthew (Matt) Poremba, Penn State University, USA, 06/2014-09/2014
Programming Languages/tools: C, C++, CUDA, Go (from Google), X10 (from IBM), Matlab, Simulink, System Generator (Xilinx), python, LaTeX, Gnuplot.
Architectural Simulators: Simplescalar, GEMS, Sniper, MARSS.
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