Sparsh Mittal

Postdoctoral Research Associate in Emerging Architectures for HPC

Future Technologies Group

Oak Ridge National Laboratory, USA.

Email: mittals at ornl dot gov

Profiles at, ResearchGate and LinkedIn


Research Interests

Overall area: Computer architecture (CPU, GPU and CPU-GPU heterogeneous systems), High-performance computing

Specific research interests: architectural simulation, energy-efficient and reliable main memory and cache design, sustainable computing, low-power computing, cache reconfiguration.

Memory technologies: SRAM, non-volatile memory (NVM) devices (STT-RAM, PCM, ReRAM), DRAM memory and eDRAM cache

Awards and Honors

1.     Received Distinguished Contribution rating at ORNL based on 2013-2014 performance appraisal. This rating recognizes the top 10 percent of staff. 

2.    My research has been covered by several technical news websites, e.g. InsideHPC 1, InsideHPC 2, Primeur Magazine, StorageSearch,, TechEnablement, ScientificComputing, ReRAM forum and HPCWire.

3.    ECpE fellowship from Electrical and Computer Engineering Department, Iowa State University, USA of $2500 in 2008.

4.    Peer Research Award from Iowa State University, USA of $200 in 2013.

5.    Topper in Electronics batch of year 2008 in ECE department at IIT Roorkee and received Institute Silver Medal for this.

6.    Institute Silver Medal for Best B.Tech project award in Electronics and Computer Engineering (ECE) Department at IIT Roorkee.

7.    Sumer Chand Jain Scholarship of INR 10,000 from IIT Roorkee.

8.     Best Student Award from High School (named MHS, Jaipur, Rajasthan, India) in 2004.


Selected Publications

1.    ACM HPDC 2014 (acceptance rate ~ 16%): Improving energy efficiency of Embedded DRAM Caches for High-end Computing Systems 

2.    ACM/IEEE Supercomputing 2014 (acceptance rate 21% Best Student Paper Session): Quantitatively Modeling Application Resiliency with the Data Vulnerability Factor

3.    IEEE ICCD 2013 (acceptance rate ~ 25%):  FlexiWay: A Cache Energy Saving Technique Using Fine-grained Cache Reconfiguration 

4.    IEEE Trans. on VLSI 2015 (impact factor 1.14): EqualWrites: Reducing Intra-set Write Variations for Enhancing Lifetime of Non-volatile Caches

5.    IEEE Trans. on VLSI 2013 (impact factor 1.14): MASTER: A Multicore Cache Energy Saving Technique Using Dynamic Cache Reconfiguration

Survey papers:

On CPU-GPU heterogeneous computing

On asymmetric multicore processors (for example, big.LITTLE-style Samsung's Exynos 5 Octa)

On power management techniques for GPUs, data centers, embedded systems, SRAM caches, DRAM main memory and PCM main memory.

On architectural techniques for near-threshold computing, data compression in cache and main memory and improving soft-error resilience in CPUs and GPUs

On architectural techniques for stacked-DRAM caches, eDRAM and NVM caches, NVMs (e.g. Flash) for storage systems and main memory, GPU caches

On question answering systems


See for full publication list and download links.

The PowerPoint slides of a few conference presentations are available here.



1.    DESTINY: DESTINY is an acronym for 3D design-space exploration tool for SRAM, eDRAM and non-volatile memory. It is a tool for modeling both 2D and 3D caches designed with five prominent memory technologies: SRAM, eDRAM, PCM, STT-RAM and ReRAM, which covers both conventional and emerging technologies. In its purpose, it is similar to CACTI, CACTI-3DD or NVSim. (Source-code, manual, DATE 2015 paper and extended technical report.). See its news coverage on ReRAM forum.

The proverb goes, write your own destiny. Hence, we have written our own [tool named] DESTINY. J

2.    Both serial and parallel versions of code of red-black SOR (successive over-relaxation) method in three state-of-the-art languages, viz. Chapel (from Cray Inc.), D (also called dlang, from Digital Mars) and Go (also called golang, from Google) can be downloaded for academic use from this link. They were used in this paper. Chapel version of the code has been incorporated in Chapel performance test suite/examples.



PhD from Iowa State University (ISU), Ames, Iowa, USA (2008-2013).

BTech from Indian Institute of Technology (IIT) Roorkee, Uttarakhand, India (2004-2008).

Professional Activity

Reviewer for: ACM Computing Surveys (2 times), ACM TACO (2 times), IEEE Intelligent Systems, IEEE ISVLSI, IEEE JETCAS, IEEE CAL (2 times), Springer Cluster Computing, Springer J. of Supercomputing, Springer book High Performance Computing in Power and Energy Systems.

Member IEEE

Student Mentoring

Matthew (Matt) Poremba, Penn State University, USA, 2014/06-2014/09

Technical Skills

Programming Languages/tools: C, C++, CUDA, Go (from Google), X10 (from IBM), Matlab, Simulink, System Generator (Xilinx), python, LaTeX, Gnuplot.

Architectural Simulators: Simplescalar, GEMS, Gem5, Sniper, MARSS.

Office Address

1 Bethel Valley Road

Building 5100, Room 229, MS-6173

Oak Ridge, TN, USA 37831-6173