Jeffrey S. Vetter
Jeffrey S. Vetter, Ph.D., is a Distinguished R&D Staff Member, and the founding group leader of the Future Technologies Group in the Computer Science and Mathematics Division of Oak Ridge National Laboratory. Vetter also holds joint appointments at the Computational Science and Engineering School of the Georgia Institute of Technology, and at the Electrical Engineering and Computer Science Department of the University of Tennessee-Knoxville. From 2009 through 2015, Vetter was the Principal Investigator of the NSF Track 2D Experimental Computing XSEDE Facility, named Keeneland, for large scale heterogeneous computing using graphics processors, and the Director of the NVIDIA CUDA Center of Excellence.
Vetter earned his Ph.D. in Computer Science from the Georgia Institute of Technology. He joined ORNL in 2003, after stints as a computer scientist and project leader at Lawrence Livermore National Laboratory, and postdoctoral researcher at the University of Illinois at Urbana-Champaign. The coherent thread through his research is developing rich architectures and software systems that solve important, real-world high performance computing problems. In particular, he has been investigating the effectiveness of next-generation architectures, such as graphics processors, massively multithreaded processors, non-volatile memory systems, heterogeneous multicore processors, and field-programmable gate arrays (FPGAs), for key applications. His recent books, entitled "Contemporary High Performance Computing: From Petascale toward Exascale (Vols. 1 and 2)," survey the international landscape of HPC.
Vetter is a Senior Member of the IEEE, and a Distinguished Scientist Member of the ACM. Vetter, as part of an interdisciplinary team from Georgia Tech, NYU, and ORNL, was awarded the Gordon Bell Prize in 2010.
Also, his work has won awards at major conferences: Best Paper Awards at the International Parallel and Distributed Processing Symposium (IPDPS) and EuroPar, Best Student Paper Finalist at SC14, and Best Presentation at EASC 2015.
In 2015, Vetter served as the Technical Program Chair of SC15 (SC15 Breaks Exhibits and Attendance Records While in Austin).
Research Projects and Software
- Check our FT Group Research Projects and Software pages, listed on our group front page for specific software packages, such as SHOC and mpiP.
- Invited, "Performance Portability for Extreme Scale High Performance Computing ," National Supercomputing Center in Guangzhou, Guangzhou, 2016.
- Invited, "Performance Portability for Extreme Scale High Performance Computing ," International Workshop on HPC Architecture, Software, and Application at an Extreme Scale @ National Supercomputing Center in Wuxi, Wuxi, 2016.
- Panel, "Opportunities for HPC based on OpenPOWER Technologies," International Workshop on OpenPOWER for HPC (IWOPH’16) @ ISC16, Frankfurt, 2016.
- Panel, "Parallel Programming," ISC, Frankfurt, 2016.
- Invited, "Exploring Emerging Technologies for Extreme Scale High Performance Computing," École Polytechnique Fédérale de Lausanne (EPFL), Geneva, 2016.
- Invited, "Understanding Portability of a High-Level Programming Model on Diverse HPC Architectures," ADAC Workshop Switzerland 2016, Lugano, 2016.
- Keynote, "Preparing for Supercomputing's Sixth Wave," ACM Symposium on High-Performance Parallel and Distributed Computing (HPDC), Kyoto, 2016.
- Invited, "Using Application-Specific Performance Models to Inform Dynamic Scheduling," 6th International Workshop on Runtime and Operating Systems for Supercomputers (ROSS), Kyoto, 2016.
- Invited, "Using Application-Specific Performance Models to Inform Dynamic Scheduling," 11th Scheduling for Large Scale Systems Workshop, Nashville, 2016.
- Contributed, "Programming Nonvolatile Memory Systems," Salishan Conference on High Speed Computing (Random Access Talk), Gleneden Beach, Oregon, 2016.
- Contributed, "Understanding Portability of a High-Level Programming Model on Diverse HPC Architectures," DOE Centers of Excellence Performance Portability Meeting, Glendale, AZ, 2016.
- Panel, "Towards Exascale Memory Systems," 17th SIAM Conference on Parallel Processing for Scientific Computing, Paris, 2016.
- Invited, "Managing the Memory Hierarchy," SOS20, Asheville, 2016.
- Invited, "Exploring Emerging Memory Technologies in Extreme Scale High Performance Computing," Forschungszentrum Julich GmbH, Julich Supercomputing Centre (JSC), Julich, 2016.
- Invited, "Managing the Emerging Complexity Wall of Extreme Scale High Performance Computing," University of Tennessee, Knoxville, Knoxville, 2016.
Recent Professional Activities
- ACM Journal on Emerging Technologies in Computing (JETC), Associate Editor, 2016 - present.
- SC, Steering Committee, 2015 - present.
- International Supercomputing Conference (ISC), Steering Committee, 2016 - present.
- SC17, Birds-of-a-Feather Chair, 2017.
- International Symposium on Performance Analysis of Systems and Software (ISPASS), Program Committee, 2017.
- Dagstuhl Seminar 17431: Performance Portability in Extreme Scale Computing: Metrics, Challenges, Solutions, Co-organizer, 2017.
- PPOPP, Program Committee, 2017.
- ISC, Research Posters, Chair, 2017.
- Exascale Requirements Review for Advanced Scientific Computing Research (ASCR), Co-chair, 2016.
- First International Workshop on Post Moores Supercomputing, Co-chair, 2016.
- SC16, Program Committee, Technical Papers, 2016.
- ICS, Program Committee, 2016.
- ISC, Program Committee, 2016.
- PMMA16, Organizing Committee, 2016.
- MODSIM, Organizing Committee, 2016.
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