Parallelized Computer System Simulators

Colloq: Speaker: 
Derek Chiou
Colloq: Speaker Institution: 
University of Texas, Austin
Colloq: Date and Time: 
Fri, 2008-02-01 10:00
Colloq: Location: 
Colloq: Host: 
Jeff Vetter
Colloq: Host Email:
Colloq: Abstract: 
Fast, full-system, computer system simulators are useful through the entire life cycle of a computer system starting at architecture, through design and verification of hardware, to BIOs, operating system, run-time system and compiler development to high-end software development. High simulator performance requires a parallel simulator, especially when simulating parallel targets but even for sequential targets. In this talk, I will describe our two inter-related approaches to parallelizing simulators. The first is FPGA-Accelerated Simulation Technologies (FAST), a methodology that parallelizes a simulator across a functional/timing partition in a way that (i) enables parallel execution for improved simulator performance and (ii) increases simulator functionality while (iii) maintains or even reduces implementation complexity. Our current cycle-accurate-capable prototype runs unmodified x86 applications on x86 Linux and Windows XP at approximately 1.2MIPS today (two to three orders of magnitude faster than Intel/AMD x86 simulators) and is expected to achieve 10MIPS over time. We are currently porting to the PowerPC ISA.<br><br>The second approach is the Research Accelerator for Multiple Processors (RAMP) collaboration that is creating the infrastructure to build 1000 core machines in FPGAs. My group is developing RAMP-White, a Linux-booting, coherent shared memory machine that will enable us to study innovative architectural, operating system and software mechanisms to better exploit parallel processing. FAST will eventually run on RAMP-White to provide cycle-accurate behavior of complex cores in a multicore system.
Colloq: Speaker Bio: 
Derek Chiou became an assistant professor at the University of Texas (UT) at Austin in January, 2005. His research areas are high performance computer simulation, computer architecture, parallel computing, Internet router architecture and network processors. His research is supported by a Department of Energy Career award, NSF and SRC and donations from Intel, IBM, Xilinx, Freescale, Altera and VMWare.<br><br>Before coming to UT, Dr. Chiou was a system architect for five years at Avici Systems, a manufacturer of high-end core routers. His responsibilities included leading all of the architectural simulation efforts, overall system architecture and component architecture including a proprietary scalable switch fabric, fabric interface chips and traffic managers.<br><br>Dr. Chiou received his Ph.D., S.M. and S.B. degrees in Electrical Engineering and Computer Science from MIT. There he was one of two chief architects of the StarT-NG and StarT-Voyager hybrid shared memory/message passing machines. He is currently a research affiliate of the MIT Computer Science and Artificial Intelligence Laboratory (CSAIL).