Performance Analysis of Fault-Tolerant Nanoelectronic Memories

Colloq: Speaker: 
Ayodeji Coker
Colloq: Speaker Institution: 
Texas A&M University
Colloq: Date and Time: 
Wed, 2008-08-13 10:30
Colloq: Location: 
5700, D307
Colloq: Host: 
Sadaf Alam
Colloq: Host Email:
Colloq: Abstract: 
Performance growth in microelectronics, as described by Moore’s law, is steadily approaching its fundamental physical limits. Nanoscale technologies are increasingly being explored as a practical solution to sustaining and possibly surpassing current performance trends of microelectronics. The fabrication and design methodologies of nanoscale technologies are still in the process of being studied and developed. The building blocks of nanotechnology are fabricated using bottom-up processes, which leave them highly susceptible to defects. Hence, it is very important that defect and fault-tolerant schemes be incorporated into the design of nanotechnology related devices. Implementing defect and fault tolerant schemes come at a performance cost. The main challenge is achieving a balance between device reliability and performance.<br><br>Our work is focused on a novel and promising class of computer chip memories called crossbar molecular switch memories and their demultiplexer addressing units. In particular, we developed a defect and fault tolerance scheme, called the Multi-Switch Junction (MSJ) scheme, for use with crossbar memories. The MSJ scheme takes advantage of the regular array geometry of the crossbar nanomemory to create multiple switches in the fabric of the crossbar nanomemory for the storage of a single bit. We conduct an in-depth analysis of the impact on performance (with respect to time delay, power, and reliability) of using the MSJ scheme with a crossbar molecular switch nanomemory and demultiplexer. Results show the MSJ scheme increases the reliability of the crossbar nanomemory and demultiplexer at a tolerable cost to delay and power performance penalty, depending on the size and degree of MSJ implementation. For example, 100% reliability can be achieved in a 16K nanomemory at a cost of 58% increase in delay and 162% increase in power requirements.
Colloq: Speaker Bio: