Architectural Techniques For Managing Non-volatile Caches
|Title||Architectural Techniques For Managing Non-volatile Caches|
|Year of Publication||2013|
|Number of Pages||68|
|Publisher||Lambert Academic Publishing (LAP)|
|Keywords||Cache architecture, Cache coloring, cache energy saving, Cache Lifetime, computer architecture, dynamic profiling, Energy efficiency, green computing, Non-volatile Memory, Phase change memory (PCM), Spin transfer torque RAM (STT-RAM), Write endurance|
As chip power dissipation becomes a critical challenge in scaling processor performance, computer architects are forced to fundamentally rethink the design of modern processors and hence, the chip-design industry is now at a major inflection point in its hardware roadmap. The high leakage power and low density of SRAM poses serious obstacles in its use for designing large on-chip caches and for this reason, researchers are exploring non-volatile memory (NVM) devices, such as spin torque transfer RAM, phase change RAM and resistive RAM. However, since NVMs are not strictly superior to SRAM, effective architectural techniques are required for making them a universal memory solution. This book discusses techniques for designing processor caches using NVM devices. It presents algorithms and architectures for improving their energy efficiency, performance and lifetime. It also provides both qualitative and quantitative evaluation to help the reader gain insights and motivate them to explore further. This book will be highly useful for beginners as well as veterans in computer architecture, chip designers, product managers and technical marketing professionals.