A Survey Of Techniques for Cache Locking
|Title||A Survey Of Techniques for Cache Locking|
|Publication Type||Journal Article|
|Year of Publication||2016|
|Journal||ACM Transactions on Design Automation of Electronic Systems (TODAES)|
|Keywords||cache locking, cache partitioning, classification, embedded system, hard real-time system, multitasking, Review, survey, worst-case execution time (WCET)|
Cache memory, although important for boosting application performance, is also a source of execution time variability, and this makes its use difficult in systems requiring worst case execution time (WCET) guarantees. Cache locking is a promising approach for simplifying WCET estimation and providing predictability and hence, several commercial processors provide ability for locking cache. However, cache locking also has several disadvantages (e.g. extra misses for unlocked blocks, complex algorithms required for selection of locking contents, etc.) and hence, a careful management is required to realize the full potential of cache locking. In this paper, we present a survey of techniques proposed for cache locking. We categorize the techniques in several groups to underscore their similarities and differences. We also discuss the opportunities and obstacles in using cache locking. We hope that this paper will help researchers in getting insights into cache locking schemes and will also stimulate further work in this area.