Cosmic Castle - DARPA Domain Specific Systems on a Chip
DARPA Domain Specific Systems on a Chip
The key innovation in this project is the ability to design and operate a DSSoC and software system holistically using precise, quantifiable performance models that are enabled by a new hardware feature, named the Performance Functional Unit (PFU). The PFU captures important performance properties of the DSSoC hardware in order to enable static and dynamic performance predictions. The PFU will also provide that information to higher-levels of the Cosmic Castle software stack at runtime to enable discovery and online decisions.
|Jeffrey Vetter (PI)||ORNLemail@example.com|
|Gokcen Kestor Gioiosa||ORNLfirstname.lastname@example.org|
|Mehmet E. Belviranli||ORNLemail@example.com|
This research is supported by the Defense Advanced Research Projects Agency (DARPA) Broad Agency Announcement (BAA) HR001117S0055 titled, “Electronics Resurgence Initiative: Page 3 Investment Architectures Thrust,” Program Area Domain-Specific System on Chip (DSSoC).
Cosmic Castle is a multi-level hardware-software strategy that is integrated by a cross-cutting performance modeling methodology, using our innovative Aspen modeling framework. Our innovative approach provides a methodology for projecting application ontologies onto programming systems, operating systems, and hardware. Specifically, Cosmic Castle develops solutions across the areas of 1) Vertically-integrated modeling of application requirements and architecture parameters using our Aspen framework; 2) Forming domain representations as ontologies using our Aspen application modeling language as a concrete method for characterizing and modeling applications; 3) Software tools to enable a development ecosystem that exercises the full capability of the highly programmable system, using Aspen models to inform decisions statically and dynamically; 4) Intelligent scheduling to manage the set of domain resources in the context of specific applications; 5) Medium access control (MAC) to interconnect the processing elements (PEs) and to allow the data throughput, taking into consideration latency, power, and other domain constraints; and 6) Hardware integration of the right set of PEs on the MAC layer with the intelligent scheduler and software into a fabricated DSSoC. Apart from domain-specific languages or extensions to existing languages, a key aspect of our approach is that we attempt to use existing programming models while developing the performance model to be as independent of the architecture as possible.